Chip Structure
- IP40
- Base Layer : P-TEOS*
- Metal Layer : TIN / AI-0.5%Cu
- Passivation Layer : HDP* / P-SiN
- IP40A
- Base Layer : P-TEOS*
- Metal Layer : TIN / AI-0.5%Cu
- Passivation Layer : P-SiO / P-SiN
*TEOS : Tetraethoxysilane
*HDP : High Density Plasma
| Specifications | IP40(Model I) | IP40A(Model I) | IP40(Model II) |
| Wafer Size | 8 inch | 12 inch | 8 inch |
| Wafer Thickness | 725±25um | 775±25um | 725±25um |
| Chip Size | 10.0mm | 10.0mm | 10.0mm |
| Pad Pitch | 40μm pitch Full Area + Staggered 250μm pitch Peripheral |
40μm pitch Staggered 250μm pitch Peripheral |
|
| Function | Daisy Chain / Bump Short Check / Vernier Breakdown Voltage Check between the Bumps |
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| Pad Config | Full Area | Peripheral | |
| Pad Size | 32 μm ♦ 110 μm ♦ | ||
| Passivation Opening | 20 μm • 100 μm ♦ | ||
| Scribe Width | 100μm | ||
| Number of Pad | 29576 pads 124 pads | 1352 pads 124 pads | |
| Number of Chip | 228 chips/wafer | 616 chips/wafer | 228 chips/wafer |
| Surface Spec of Round | Electroless Ni/Au plating | ||
| • Top Side ♦ Bottom Side | |||
