Chip Structure

  • Base Layer : P-TEOS*
  • Metal Layer : TiN / AI-0.5%Cu
  • Passivation Layer : HDP* / P-SiN

*TEOS : Tetraethoxysilane
*HDP : High Density Plasma



Wafer Size 8 inch
Wafer Thickness 725±25um
Chip Size 3.0mm ♦
Pad Pitch 60/55/50/45/40/35/30/25/20
Metal Thickness 0.6μm or 0.8μm
Function Daisy Chain
Pad Config Peripheral
Electrode Wire Bonding
Pad Size (57×110μm) (52×110μm) (47×110μm)
(42×110μm) (37×110μm) (32×110μm)
(27×110μm) (22×110μm) (17×110μm)
Passivation Opening (53×100μm) (48×100μm) (43×100μm)
(38×100μm) (33×100μm) (28×100μm)
(23×100μm) (18×100μm) (13×100μm)
Scribe Width 100μm
Number of Pad (40×4) (40×4) (38×4)
(38×4) (36×4) (34×4)
(30×4) (26×4) (18×4)
Number of Chip 3016 chips/wafer
  ♦ Bottom Side

IPC Validation Services

New Product

.4mm Pitch eWLP Dummy Wafer-Amkor
.4mm Pitch eWLP Dummy Wafer-Amkor


Technical Center

In the News

Practical Components’ Publishes New 2017 Product Catalog
This catalog marks a major revision to the Practical Components catalog. Inside you will find over 20 pages of new products and for the first time much of it is printed ... [read more]

Request Catalog


Request or download our catalog and sign-up for our newsletter.